Bisync Protocol Tutorial

By Charles A. Wilde, CTO and Chief Software Architect of Aton International, Inc.

This tutorial will give you a detailed view into the nature of the legacy IBM Bisync protocol. It is cast in the description of a Bisync frame I/O driver for the many variants of the Zilog SCC, SIO or Intel 8274 USART communication IC’s.

Charles A.Wilde originally wrote this document in 1987. It was last updated in 2004. It is still a much requested document. We have re-published it on our website to accomodate the needs of IT professionals and students who need this information.

The source code for this I/O driver is available. Please contact us if you would like more information about purchasing it.

Overview
BISYNC Station Modes
Mode Transitions
Driver Interface
Completion Code
Block Terminating Character
LGR Count
Operation Code
Control Mode Receive
Block Receive
Block Receive State Machine
Time-out Operation for Receive Block
Block Transmit
Block Transmit State Machine
EIA (RS-232) Interface Considerations

1. Overview

There really is no such thing as the “IBM BISYNC protocol”. But there are many IBM devices and programs that use a general set of conventions for BISYNC described in the IBM publication General Information – Binary Synchronous Communications GA27-3004-2.

The actual protocol used varies significantly from device to device or program to program, so one needs to talk in terms of 3270 BISYNC or 2780 BISYNC, HASP, etc. Also the concepts of layering and protocol stacks were still in formation during the era when BISYNC was designed, so finding a clear dividing line between various layers in BISYNC is difficult at best.

It is, however, possible to create a BISYNC I/O driver to input or output transmission blocks that will serve all of the IBM variants of BISYNC. The device specific protocol handler (3270, 2780, HASP, etc.) then uses the I/O driver to send and receive BISYNC transmission blocks.

An implementation of such a BISYNC transmission block I/O driver is described below in detail.

2. BISYNC Station Modes

A BISYNC station is in one of four modes:

Circuit verification mode
Control mode
Text mode master
Text mode slave

The circuit verification mode is a variation of control mode used only for switched line connections. In the initial exchanges, the ENQ, ACK or NAK sequences are preceded by 2 to 15 leading graphic characters. These leading graphics are used to identify the calling and answering stations. Once both stations agree (based on the graphics exchanged) that the switched connection should continue, the leading graphics are not used in subsequent control mode exchanges.

The control mode is the initial mode and the idle mode that is returned to when the line connection is maintained and no text messages are in the process of being transferred. In point to point mode, control mode consists of the line bid (ENQ followed by ACK0, WACK or NAK). In centralized multi-point operation, control mode consists of a poll (id, ENQ) or select sequence (id, ENQ followed by ACK0, WACK or NAK).

The text mode master is the station sending text and the text mode slave is the station receiving the text. The master and slave in this context switches back and forth between the host (e.g. mainframe) and the terminal (e.g. 3270, 2780) depending on the direction of the flow of data or text.

After circuit verification mode is complete, the station moves to control mode, and from control mode moves to master and slave modes based on protocol sequences. The station moves freely amongst the control, master and slave modes many times during a typical session but will return to circuit verification mode only if the connection is broken or disconnect (DLE EOT) is transmitted or received on a switched line.

3. Mode Transitions

A station moves from circuit verification mode to control mode after the station id sequences described above are exchanged. The circuit verification mode serves as control mode in establishing master or slave mode.

The station does not return to circuit verification mode until either the circuit is broken or a DISC disconnect sequence (DLE EOT) is transmitted or received.

The station moves from control mode to master mode upon receipt of a poll sequence (centralized multi-point) and it responds with a text block. The station remains in control mode if it has no traffic and responds to the poll with EOT.

The station moves from control or circuit verification mode to master mode upon receipt of a positive acknowledgment (ACK0) to a line bid (point to point) and it responds with a text block. The station remains in control mode if it did not receive ACK0 to its line bid.

The station moves from control mode or circuit verification mode to slave mode upon receipt of a selection sequence (multi-point) or line bid (point to point) and it responds with ACK0. It remains in control mode or moves from circuit verification mode to control mode if it responds with NAK. It remains in either control mode or circuit verification mode if it responds with WACK.

The station moves from master mode to slave mode if it receives a text block as a reply to a text block it has transmitted (conversational reply) instead of the usual ACK0, ACK1, NAK or ENQ. The station remains in master mode if it receives ACK0, ACK1, NAK or ENQ or transmits ENQ for a missing or garbage reply. The station moves from master to control mode if it either transmits or receives EOT.

The station moves from slave mode to master mode if it has just received a text block and transmits a text block (conversational reply) in lieu of ACK0, ACK1, NAK or ENQ. The station remains in slave mode if it transmits ACK0, ACK1, NAK or ENQ in response to the block it just received. The station moves from slave to control mode if it either transmits or receives EOT.

4. Driver Interface

The interface between the protocol handler and the I/O driver consists of:

Operation code
Transmission block buffer
Completion code
Block termination character
Leading graphic (LGR) count

The transmission block buffer contains the entire transmitted or received block except that leading pad, SYN (or DLE SYN in transparent mode), block check BCC, and trailing pad characters are supplied by the driver on transmission and stripped by the driver on receive. All other characters, including combinations such as DLE DLE, ITB, STX, ETX, etc. are stored in the block buffer.

There is no specific maximum block size limit imposed on blocks received from the mainframe, although 8192 bytes is a practical limit that is not exceeded in normal practice. The 3270 does not transmit blocks larger than 256 bytes. The block buffer is implemented as a circular buffer.

Actually there are two block buffers, one for transmit and one for receive. BISYNC provides a technique called conversational reply, commonly used in 3270 applications, that allows the receiver of a block to send another text block in reply instead of ACK. Thus the BISYNC driver transmits data from a buffer created by the protocol handler and stores data in a circular buffer for received data as it comes in.

5. Completion Code

The completion code is a collection of bits that signals the progress of the I/O request and the significant events that occurred during the request.

Request incomplete
Leading graphics received
Block check error
Trailing pad error (First 4 bits of pad not ones)
USART receiver overrun
Parity error (ASCII line code only)
Buffer overrun/underrun or buffer overrun
Missing block terminating character (time-out)
Missing ETB/ETX character (time-out)
Invalid SCC character (character after DLE)
Invalid control sequence
DCD/CTS error
DSR lost

6. Block Terminating Character

The block terminating character (BTC) is the last significant character received that signaled the end of the block. This character can be:

ETX or DLE ETX
ETB or DLE ETB
ENQ or DLE ENQ
EOT or DLE EOT
NAK
DLE RVI
DLE WACK
DLE ACK0
DLE ACK1
DLE “Stick”

If the BTC is a two character sequence starting with DLE, then the BTC is encoded using the second character with the high order bit set. Note that if text mode was started by SOH, STX or DLE STX, only a BTC of ETX, DLE ETX, ETB, DLE ETB, ENQ or DLE ENQ will be recognized to terminate the block. Other BTC’s will be stored in the buffer, the “Invalid control sequence” bit will be set in the completion code and the receive operation continues.

7. LGR Count

This is the number of leading graphic characters received for the current block.

8. Operation Code

The operation code signals are of four operations the driver is capable of:

Control mode receive
Transmit
Receive
Transact (Transmit then Receive)

There are three basic operations for the driver: control mode receive, block receive and block transmit. There are enough special considerations to justify differentiating a block receive in control mode and a block receive in master or slave modes.

The transact operation code is frequently used and means just to automatically follow block transmit by block receive. Some mainframe communication front end controllers in certain situations will turn the line around very fast, which means that they will start sending the reply to transmission block within one or two character times after receiving a trailing pad. It’s important that the local USART be switched to receive as quickly as possible after transmission, particularly at high bit rates. If the separate transmit and receive operations are used by the protocol handler, the USART receiver setup time may get unacceptably long.

The driver always returns to the caller (protocol handler) almost immediately. The driver sets up the USART for receive or transmit and, in the case of transmit, outputs the first character. All other data transfers occur under interrupt control. The calling program can monitor the state of the receive or transmit operation via the completion code. The “Request incomplete” bit will be cleared when the interrupt handler processes the last character or times out.

This technique allows background processing while block transmit/receive is in process and it also allows the protocol handler to abort a receive operation with a transmission if necessary. For instance, in point to point mode, the idle state is control mode receive, waiting for a line bid. When text is to be transmitted, the protocol handler can abort the receive and generate an outgoing line bid using the transact operation code.

9.Control Mode Receive

In multi-point control mode, the poll or select sequence is immediately preceded by an EOT sequence. The USART must be placed into Hunt mode (sync search) immediately after the EOT is received so that the poll or select will not be missed.

If the station was in slave mode and transmitted EOT to signal an abnormal condition and return to control mode, it is possible that the other station missed this EOT and will transmit ENQ to ask for a retransmission of the EOT. The protocol handler needs to recognize this ENQ as an error recovery attempt and not as a line bid.

The control mode receive function is terminated only when a valid ENQ sequence is received. This may be the ENQ without leading graphics as a line bid in point to point or in the error recovery case mentioned above, or with leading graphics as in a multi-point poll or select sequence. If leading graphics exist they are at least two and less than 16 characters. The graphics characters are in the range of hexadecimal 40 through FE for EBCDIC or 20 through 7E for ASCII. The ENQ and any leading graphics are in the receive block buffer at the end of the control mode receive operation. A trailing pad check is performed. The low order 4 bits of the character following the ENQ must be all ones. Any SYN characters are discarded.

The control mode receive operation starts with hunt mode and hunt mode is reentered whenever the following conditions occur:

A control character other than SYN or ENQ is received. Control characters are 00 through 3F or FF hex for EBCDIC or 00 through 1F or 7F for ASCII. Note exceptions for transparent monitor mode below.
The low order 4 bits of the character following the ENQ are not ones.
More than 15 leading graphics are received.
Exactly one leading graphic is received.

In control mode on a multi-point line, it is necessary for a tributary station to monitor for transparent text blocks. The transparent data may contain a sequence that looks exactly like a poll or select and trigger a response that would garble the rest of the block for the station actually receiving the transparent data. Thus when the control mode receive process detects STX, SOH or DLE STX, it calls the block receive driver function to process the block. The block receive function knows that the control mode receive function has been called so it doesn’t store the data in the receive block buffer and returns to the beginning of the control mode receive routine at the end of the block. This technique is termed “transparent monitor mode”.

10. Block Receive

The block receive op code copies a data block from the USART into the receive buffer when the station is in master or slave modes. It also processes a data block starting with STX, SOH or DLE STX when the station is in control mode. In this last case (transparent monitor mode), data is not stored in the receive buffer, but all other actions occur normally, and when this block receive routine finishes the block, it returns to the beginning of the control mode receive routine where the USART begins hunt mode.

From the BISYNC driver’s point of view there are six basic block formats:

EOT
LGR ENQ
LGR NAK
LGR DLE SCC
STX/SOH … text … ETX/ETB BCC
STX/SOH … text … ENQ

Each of the six block formats have leading SYN characters preceding the characters shown and have trailing pad characters (hex FF) following them. The leading SYN characters may themselves be preceded by leading pad characters (hex 55). The leading pad characters are automatically discarded by the USART during hunt mode. The leading SYN characters are discarded by the USART hunt mode and by the USART Sync Character Load Inhibit function. The USART Sync Character Load Inhibit function must be turned off when the first character of text is received so that BCC calculation will be done correctly.

The first trailing pad is checked to see that the low order 4 bits are ones. If not, the “Trailing pad error” bit is set in the completion code.

The EOT, ENQ, NAK, DLE, STX, SOH, ETX and ETB characters shown in the six block formats are EBCDIC or ASCII characters that retain their standard BISYNC definitions.

The driver clears text mode and transparent text mode when starting a block read command and will set text mode when encountering an STX, SOH or DLE STX sequence. It will set transparent text mode when encountering a DLE STX sequence. Once set, text mode remains set until the end of the block. The transparent text mode is cleared by DLE ITB or the end of block. The driver treats certain characters differently in text mode, as described below.

LGR is zero or two to 15 leading graphic characters. A graphic character is in the range of hex 40 through FE for EBCDIC and 20 through 7E for ASCII. To make the driver simpler, it will accept LGR on any of the six frame formats and will set the “Leading graphics” bit in the completion code. It is up to the protocol driver to determine if the leading graphics are appropriate in the current context and that the number of leading graphics is correct. All leading graphics received are stored in the receive buffer (even if more than 15) and a count of the number of leading graphics characters received is returned in the LGR count word of the I/O driver interface.

SCC is the secondary control code, or the character immediately following the DLE. The SCC can be a normal control character (STX, ETB, ETX, SYN, ENQ, DLE, ITB or EOT) or it can be a “stick” character (RVI, WACK, ACK0 or ACK1). An SCC other than these twelve will cause the “Invalid SCC” bit to be set in the condition code. In transparent mode, the SCC must be preceded by the proper number of DLE characters to be recognized as an SCC. For instance:

DLE STX DLE DLE ETX DLE ETX

The DLE DLE signals a single text character of DLE so the first ETX is treated just as a text character and not as an SCC. The second DLE ETX acts as the block terminator.

The “… text …” shown in the last two of the six block formats can contain control characters that require special processing. SYN characters are discarded, not stored in the receive buffer and not included in the block check calculation. ITB characters are stored in the buffer and included in the block check. The two characters (one if ASCII) after the ITB are BCC characters which are not stored in the buffer. After the ITB and BCC characters, text continues. If transparent text was active when DLE ITB was encountered, then normal text is active after ITB until DLE STX occurs. Thus STX is optional after ITB since normal text mode is active. If ITB is encountered in non-text mode due to transmission error, the ITB BCC sequence is processed as if in text mode, then non-text mode resumes until SOH, STX or DLE STX is encountered.

In text mode some control characters which would terminate the block in non-text mode are stored in the buffer and do not cause the block to terminate. The “Invalid BTC character in text mode” bit of the condition code is set in this case.

The BTC sequences which do not cause termination in text mode are EOT, NAK, DLE EOT, DLE RVI, DLE WACK, DLE ACK0, DLE ACK1 or DLE followed by an undefined SCC code. After the first STX or SOH, subsequent STX or SOH characters are treated as normal data characters.

Both characters of the sequence DLE STX are stored in the buffer and start the transparent text mode which lasts until DLE ETX, DLE ETB, DLE ITB or DLE ENQ is found. When in transparent mode, all characters, including all control characters except DLE are treated as normal data and stored in the receive block buffer. Certain control characters preceded by a DLE character are given special treatment.

DLE SYN is used for time fill and periodically to avoid a time-out. The sequence is stripped and not stored in the buffer.

DLE DLE is used to indicate a single DLE. The character after the second DLE is not given special treatment unless it is also a DLE character. Both characters are stored in the buffer.

DLE ETB, DLE ETX, DLE ENQ and DLE ITB perform the same function as ETB, ETX, ENQ and ITB in normal text mode. DLE ITB also causes an exit from transparent mode. Both characters of the DLE SCC sequence are stored in the buffer.

BCC is the block check character(s). In ASCII a single BCC character is used (VRC/LRC). In EBCDIC a two character CRC-16 code is used. The ASCII mode with transparency installed (VRC/CRC) along with 6-bit trans code (SBT) are not used in IBM products of current interest so no further consideration is given to them. The BCC characters occur after ETB, ETX or ITB in normal text or after DLE ETB, DLE ETX or DLE ITB in transparent mode. Text will continue on after ITB or DLE ITB and the BCC checker will be cleared if the current BCC is received after ITB or DLE ITB. If a BCC error is sensed after the BCC characters are received, the “Block check error” bit of the condition code is set. The BCC characters are not stored in the buffer.

Not all characters are included in the block check. The following characters or sequences are excluded:

All characters which precede the first SOH, STX or DLE STX control sequence of a text block.
The first STX, SOH or DLE STX which initiates text mode clears the block check accumulator which effectively excludes the first STX, SOH or DLE STX and all characters preceding it.
All SYN characters in normal text mode.
All DLE SYN sequences in transparent t
ext mode when SYN is an SCC.
The first DLE character of a DLE control sequence, either valid or invalid, if in transparent text mode.

The characters or sequences that are included are:

All non-control characters.
All SOH or STX characters which follow the initial SOH, STX or DLE STX characters which initiate normal or transparent text mode.
If in normal (non-transparent) mode, all ITB, ETB, ETX or DLE characters transmitted during or at the end of the text block.
EOT and NAK should not be in a normal text block, but if they are, they are treated as normal text characters and included in the block check.
In normal text mode, DLE is treated as a non-control character so it and the SCC characters following it (other than STX) are included in the block check, whether or not the DLE SCC is a valid sequence. As indicated above, if no SOH, STX or DLE STX characters have been encountered, then both characters of DLE STX and all characters preceding them are excluded from the block check, and then transparent mode is entered. If an SOH or STX has been encountered and normal text mode is in progress, both the DLE and STX characters are included in the block check and transparent mode is entered.
In transparent text mode, the DLE of a DLE SCC sequence is excluded in the block check, but the SCC (valid or invalid) is always included unless it is SYN.

A valid ENQ or DLE ENQ sequence unconditionally terminates a block, and the final block checking is not done nor is BCC transmitted. The ENQ or DLE ENQ must be followed by a valid PAD (low order 4 bits are ones) to be recognized as a BTC. If the character following the ENQ or DLE ENQ does not have ones in the low order 4 bits, then the ENQ is treated as a data character and included in the block check, and the DLE is included in normal mode or excluded if in transparent mode, and the text receive process continues. It should be noted that an idle line (marking) generates trailing pad (hex FF) characters in the receiver. Disabling the transmitter on the USART holds the line in marking or idle state.

A basic design goal in IBM Bisync is to not prematurely terminate the receive operation because noise on the communication line turned some data character into a stop character such as EOT, NAK or ETX. Several techniques are used to accomplish this:

- Some stop characters or sequences are simply not recognized in text mode. Only three sequences can stop text mode – ETX, ETB or ENQ (DLE ETX, DLE ETB or DLE ENQ). All other stop sequences such as EOT, NAK, DLE WACK, etc. are simply treated as data characters.
- A stop sequence such as EOT, NAK, DLE RVI, DLE WACK, etc. is recognized in non-text mode only if they are followed by a trailing pad, otherwise the receive operation goes on.
- The idea here is that it is better to let the receive operation go on, to be terminated by the three second time-out, rather than taking the chance of terminating early in the middle of a transparent block and subsequently erroneously receiving what looks like an ACK, EOT, addressing sequence, etc.

An ETX or ETB will act as a stop character even in non-text mode because a relatively common error is for the STX or SOH to be corrupted, causing text mode not to be entered.

Because the first SOH, STX or DLE STX sequence is not included in the CRC, and you don’t really know which one of the three you received, it is common to rely on the character following the SOH, STX or DLE STX to determine if the block has a header or not. For instance, the 3270 always follows an SOH with the “%” character when transmitting status or test messages. The first character of the first message block starting with STX is the poll address, which is never validly the character “%”.

11. Block Receive State Machine

The operation of the driver in the receive block mode can be summarized by looking at how it reacts to each type of character received. In the description to follow, “store” means if the circular buffer is already full. If so, then set the “Buffer overrun” bit and clear the “Request incomplete” bit in the completion code. If space in the circular buffer is available, then the driver places the character just received into the circular buffer and increments the block size.

If non-text mode is still active when the circular buffer is filled, then set the “Invalid control sequence” bit in the completion code. The receive operation continues, but no further data is stored in the block buffer.

“Include in CRC” means to turn on Receive CRC Enable bit, and “Exclude in CRC” means to turn off Receive CRC Enable bit, which is bit 3 of WR3 in the 8274 USART.

The “Sync Character Load Inhibit” bit 1 of WR3 in the 8274 is set when hunt mode is started, but it must be cleared when text mode is entered or the CRC calculation may be incorrect.

Several state counters and flags are defined to control the receive process:

Block State Pointer (BSP)
- - 0 – Non-text mode (initial state)
  - 1 – Normal text mode
  - 2 – Transparent text mode
  - 3 – Intermediate BCC #1
  - 4 – Intermediate BCC #2
  - 5 – Final BCC #1
  - 6 – Final BCC #2
  - 7 – Final BCC #3
  - 8 – Final BCC #4
  - 9 – Trailing pad check
DLE Flag
BCC Delay Counter
Previous Text Mode

When the block receive routine is started, the BSP is set to zero, the DLE flag is cleared and the BCC delay counter is set to zero. The USART is put into receive mode.

The DLE flag is cleared whenever processing for an incoming character is finished (i.e., just before interrupt exit), unless the DLE flag was set by the current character (DLE).

Regardless of what character code has been received or the state of BSP, if the BCC delay counter is not zero, then decrement it. If it then reaches zero, check the CRC/Framing error bit in the 8274 USART register RR1, bit 6. If the bit is set, then set the “Block check error” bit in the completion code. If the bit is not set, then do not change the “Block check error” bit in the completion code.

If the BSP is 0, 1 or 2, then actions are based on the character code received. If the DLE flag is set and (BSP is not 2 or the character is not SYN), then store DLE in the buffer. Otherwise a transparent idle (DLE SYN) has been received, which is not stored in the buffer nor included in the CRC.

SOH. Include in CRC and store. If DLE flag is set, then set “Invalid SCC character” bit in the completion code. If BSP is 0, then set BSP = 1, reset the CRC checker in USART (WR0 bits 6-7 = 01), turn off “SYNC character load inhibit” in USART (WR3 bit 1) and exclude in CRC.
STX. Include in CRC and store. If BSP is 0, reset CRC checker in USART, turn off “SYNC character load inhibit” in USART, exclude in CRC and set BSP = 1. If DLE flag is set, then set BSP = 2.
ETX. Include in CRC and store. If DLE flag is set, set BTC to DLE ETX, else set BTC to ETX. If BSP is 0, then set “Invalid control sequence” bit in the completion code. If BSP is not 2 and DLE flag is set, then set “Invalid SCC character” bit in the completion code. If BSP is not 2 or (BSP is 2 and DLE flag is set), then save BSP in previous text mode and set BSP = 5.
DLE. If DLE flag is set or BSP is not 2, then include in CRC and store, else exclude from CRC and do not store. If DLE flag is not set, then set it. The DLE flag is cleared whenever processing for an incoming character is finished (i.e., just before interrupt exit), unless the DLE flag was set by the current character (DLE). Thus the DLE flag will be set for the character following the DLE (the SCC) and then cleared. The character after the SCC may be DLE, which will again set the DLE flag.
ITB. Include in CRC and store. If BSP is 0, then set “Invalid control sequence” bit in the completion code. If DLE flag is set and BSP is not 2, then set “Invalid SCC bit” in the completion code. If BSP is not 2 or (BSP is 2 and DLE flag is set), then if BSP is 2, set BSP = 1, save BSP in previous text mode and set BSP = 3.
ETB. Include in CRC and store. If DLE flag is set, set BTC to DLE ETB, else set BTC to ETB. If BSP is 0, set “Invalid control sequence” bit in the completion code. If BSP is not 2 and DLE flag is set, then set “Invalid SCC character” bit in the completion code. If BSP is not 2 or (BSP is 2 and DLE flag is set), then save BSP in previous text mode and set BSP = 5.
ENQ. Include in CRC and store. If BSP is not 2 and DLE flag is set, then set “Invalid SCC character” bit in the completion code. If DLE flag is set, then set BTC to DLE ENQ, else set BTC to ENQ. If BSP is not 2 or (BSP is 2 and DLE flag is set), then save BSP in previous text mode and set BSP = 9.
SYN. If BSP is 2 and DLE flag is not set, then include in CRC and store, else exclude from CRC and do not store. If DLE flag is set and BSP is not 2, then set “Invalid SCC character” bit in the completion code.
EOT. Include in CRC and store. If DLE flag is set, then set BTC to DLE EOT, else set BTC to EOT. If BSP is 0, save BSP in previous text mode and set BSP = 9. If BSP is 1 or (BSP is 2 and DLE flag is set), then set “Invalid control sequence” bit in the completion code.
NAK. Include in CRC and store. If DLE flag is set, then set BTC to DLE NAK and set “Invalid SCC character”, else set BTC to NAK. If BSP is 0, then save BSP in previous text mode and set BSP = 9. If BSP is 1 or (BSP is 2 and DLE flag is set), then set “Invalid control sequence” bit in the completion code.
“Stick” character. A group of SCC characters that will cause receive operation to stop if not in text mode and DLE flag is set. In EBCDIC a stick character is hex 60 through 7F. In ASCII a stick character is hex 30 through 3F and must have odd parity to be recognized as “stick”. Include in CRC and store. If DLE flag is set, set BTC to DLE “Stick”. If BSP is 0 and DLE flag is set, then save BSP in previous text mode and set BSP = 9, else set “Invalid control sequence” bit in the completion code. Four of the 32 (EBCDIC) or 16 (ASCII) stick characters are defined as ACK0, ACK1, RVI and WACK. The others will be declared as errors when the protocol handler examines the BTC character code. The term “stick” refers to a column (two columns) in the EBCDIC code table.
All other characters. Includes “stick” characters (where DLE flag is not set), but excludes all other characters specifically mentioned above. Include in CRC and store. If graphic character (EBCDIC, hex 40 through FE; ASCII, hex 20 through 7E) and BSP is 0, then set “Leading graphics received” bit in the completion code and increment leading graphics (LGR) counter.

If the BSP has a value of 3 through 9, actions are based on the BSP and not on the character code received.

If the BSP is 3 or 5:

- . Include in CRC
- . Discard the character – no store
- . Increment BSP
- . Set BCC delay counter to 3

If the BSP is 4 or 6:

- . Include in CRC
- . No store

If the BSP is 4, set BSP = previous text mode

If BSP is 6, set BSP = 7

If the BSP is 7:

If the low order 4 bits of the received character are not ones, set the “Trailing pad error” bit in the completion code.

- . Include in CRC
- . No store
- . Set the BSP = 8

If the BSP is 8:

- Clear the request incomplete bit in the completion code. This last character time gives the CRC checker the time it needs to complete its calculation.
- No store
- Include in CRC. Actually it doesn’t matter whether or not you include characters from BSP 7 and 8 in the CRC since the CRC error status will be sampled before these two characters shift their way into the CRC accumulator. Also note: The CRC character cannot be reset after the BCC bytes following an ITB because of the two character time delay and because text is still being received. This is no problem since if there is no transmission error, the CRC accumulator will be zero after the two BCC bytes have been received. If there was an error, the code described above for the BCC delay counter will set the block check error bit in the completion code and further checking is irrelevant. Also note that for the Intel 8274 USART, two of the three bytes of the receive FIFO are useless for practical purposes in BISYNC when the USART’s CRC checker is being used. This is because the decision about whether to include or exclude the character from BCC must be made before a second character stacks up in the FIFO. If the driver waits too long to retrieve the character from the USART, the error won’t be known until the end of the block when a block check error will probably be seen.

If the BSP is 9:

- If the low order 4 bits of the received character are one, then clear the “Request incomplete” bit in the completion code, else include in CRC, store, set “Invalid control sequence” bit in the completion code and set BSP back to the previous text mode.

12. Time-out Operation for Receive Block

The receive block operation will be terminated with the “Request incomplete” bit cleared and the “Missing block terminating character (time-out)” bit set in the condition code if:

- a) In non-text mode, a valid BTC has not been received within 3 seconds of the start of the receive operation.
- b) In text mode, 2 seconds have elapsed since the last sync sequence (SYN SYN for normal text, DLE SYN for transparent text).
- c) A continuous sequence of SYN (non-transparent) or DLE SYN (transparent text) characters have been received for over 3 seconds.
- d) A receive interrupt doesn’t occur for 3 seconds.

These time-outs can be accomplished by starting the 3 second timer at the beginning of the receive block operation and restarting the time-out if:

- a) SOH, STX or DLE STX causes transition from non-text mode to text mode (BSP goes from 0 to 1 or 2).
- b) In text mode, a transition from sync sequence (SYN SYN or DLE SYN) to a character not part of a sync sequence. A single SYN character is not recognized as a sync sequence for purposes of resetting the timer, although it will not be stored or be included in the CRC while in normal text mode. The timer is stopped when the “Request incomplete” bit in the completion code is cleared.

A separate 2 second timer needs to be set when text mode is entered and retriggered each time a sync sequence (SYN SYN or DLE SYN) is received. If this timer expires, the “Missing ETB/ETX character (time-out)” bit is set and the “Request incomplete” bit is cleared in the completion code.

A separate timer needs to be set at the beginning of the receive operation and retriggered each time a data character is received from the USART interrupt routine. This will allow recovery if carrier detect (DCD) doesn’t come up or is lost. With the auto-enables mode (USART WR3, bit 5) set, receive interrupts won’t occur if carrier detect is not present. It will also allow recovery if an interrupt gets “lost” for any reason. If this timer runs out, the “DCD/CTS error” bit of the completion code is set, and the “Request incomplete” bit is cleared.

13. Block Transmit

Block transmit is the inverse of block receive, and most of the general discussion given under the block receive description above applies here. In particular, the block buffer contents will be the same. The protocol handler must supply all control codes such as STX, SOH, DLE STX, DLE DLE, etc. Block transmit will supply only leading pads, synchronization and time fill sequences (SYN SYN or DLE SYN in transparent mode), BCC characters after ITB, ETB and ETX, and the trailing pad character. All other sequences must be in the transmit block buffer. The driver will transmit all characters in the buffer given by the count (which can be zero). The driver only stops when all characters in the block are output and a “stop” character was output as the last character of the block; thus several messages can be concatenated.

A stop character is one which causes the BSP state 5 (trailing pad generate) to be set. In non-text mode these are NAK, ENQ, EOT, DLE “stick.” In normal text mode, the stop characters are ETB, ETX and ENQ. In transparent text mode, the stop characters are DLE ETB, DLE ETX and DLE ENQ.

If all blocks in the buffer are exhausted and a stop character wasn’t found, then sync idles are output until another buffer is given to the driver. Sync idle is DLE SYN if in transparent text mode, SYN otherwise. If two seconds of continuous sync idles have been output and no more buffers are given to the driver, then the transmission is aborted (with DLE ENQ if in transparent mode, else ENQ), trailing pad is output, the “Buffer overrun/underrun” bit is set and the “Request incomplete” bit is cleared in the completion code.

During polling, an EOT (line reset) is output just before the poll, so the transmit buffer would contain:

EOT TPD LPD SYN SYN a a b b ENQ

The driver outputs the leading pads and syncs before the EOT and a trailing pad after the ENQ. The trailing pad (TPD – FF hex) after the EOT, the leading pad (LPD – 55 hex) and leading syncs (SYN) before the poll address must be placed in the transmit buffer by the protocol handler.

Some additional parameters in the driver/protocol handler interface apply only to block transmit:

Leading pad count
Leading SYN count

A BCC output flag is added for USART control, and the block state pointer (BSP) modes for block transmit are as follows:

0 – Non-text mode
1 – Normal text mode
2 – Transparent text mode
3 – ITB #1
4 – ITB #2
5 – Trailing pad generate
6 – Leading pad generate (Initial State)
7 – Leading SYN generate

The number of leading pad (hex 55) and sync characters can be varied depending on the application. Some modem or communication links require more of these characters than others for reliable operation. The leading pads supply bit phase information for certain types of modems. Normally one leading pad and two SYN characters are used. On some channels the number of leading pads and SYN characters need to be increased for reliable operation. The counts can be set to zero if no leading pads are desired or the protocol handler wishes to format these characters in the block buffer.

When the block transmit routine is started, the BSP is set to 6, previous text mode is set to 0 and the DLE flag is cleared. The USART is put into transmit mode and the first interrupt is simulated by calling the interrupt processing routine. The USART will not interrupt until the first character moves from the transmit buffer to the transmit shift register.

The DLE flag is cleared whenever processing for an outgoing character is finished (i.e., just before interrupt exit), unless the DLE flag was set by the current character (DLE) removed from the transmit buffer.

If the BSP has a value of 6, the leading pad characters (hex 55) are output. The leading pad count is decremented and when it reaches zero, BSP is set to 7. The leading pad count may initially be zero, in which case no leading pads are output and BSP is set to 7. If driver is configured for new sync (full duplex 4 wire central station for multi-drop) operation, the “new sync” signal (RS-232 Pin 14) is enabled just before the first leading pad is output.

If the BSP has a value of 7, then leading SYN characters (hex 32 for EBCDIC or hex 16 for ASCII) are output. The leading SYN count is decremented and when it reaches zero, BSP is set to previous text mode. The leading SYN count may initially be zero, in which case no leading SYN’s are output and BSP is set to previous text mode.

If BSP is 0, 1 or 2, the driver actions are based on the character code removed from the transmit buffer.

Before a character is removed from the buffer, however, the sync idle timer is checked. This timer expires and retriggers every one second if in normal text mode or external (modem) clocking is used, or expires and retriggers for every 64th character removed from the transmit buffer if in transparent text mode and internal (business machine) clocking is used. Each time the timer expires a sync idle sequence is inserted in the character stream. If BSP is 0 or 1, the leading SYN counter is set to 2, BSP is saved in previous text mode and BSP is set to 7, causing two SYN characters to be inserted in the transmit character stream. If BSP is 2, the leading SYN counter is set to 1, BSP is saved in previous text mode, a DLE character is output and BSP is set to 7, causing a transparent DLE SYN sequence to be inserted in the character stream

14. Block Transmit State Machine

The operation of the driver in the transmit block mode can be summarized by looking at how it reacts to each type of character removed from the buffer. In the description to follow, “load” means to place a character in the USART buffer in response to a transmit interrupt. Before removing a character from the block buffer, the driver checks the number of remaining characters. If it is zero, then transmission is complete. Turn off transmitter enable in the USART (transmit data goes to marking which looks like a trailing pad (hex FF) after the character in the transmit shift register (hex FF) is clocked out), and if half-duplex two wire operation, turn off RTS as well. If the driver is configured for new sync operation, the “new sync” signal is turned off at this point (first trailing pad is just starting to get onto the transmission line). If the transact operation code is in effect, start the receive block routine, else clear the “Request incomplete” bit in the completion code.

The term “Include in CRC” means to turn on the Tx CRC Enable bit; “Exclude in CRC” means to turn off this bit, which is bit 0 of WR5 in the USART. It is important that this bit be turned off when transmission is started and that it be kept off until text mode is started by SOH, STX or DLE STX so that the CRC generator reset will be done properly.

SOH. If BSP is 0, then exclude in CRC, reset CRC generator, set USART registers WR6 and WR7 to SYN SYN, and set BSP = 1; else include in CRC.

STX. If BSP is 0, then exclude in CRC, reset CRC generator, set USART registers WR6 and WR7 to SYN SYN, and set BSP = 1; else include in CRC. Load. If DLE flag is set, then set BSP = 2 and load DLE SYN into USART registers WR6 and WR7.

ETX/ETB. Include in CRC and load. If BSP is 2 and DLE flag is not set, then treat as normal data; else set BSP = 5. Output “Reset Tx Underrun/EOM Latch” and “Reset Tx Int/DMA Pending” commands to USART register WR0, set the sync registers WR6 and WR7 to hex FF and set the BCC output flag. Subsequently, a USART external status interrupt will occur when the Tx shift register is empty and the CRC is loaded. The BCC output flag in conjunction with the “Tx Underrun/EOM” status bit (RR0 bit 6) will inform the external status interrupt service routine to treat the external status interrupt as if Tx buffer empty interrupt had occurred. Otherwise, the external status interrupt routine just samples external status and aborts the operation if CTS or DSR is lost.

DLE. If BSP is not 0 and (DLE flag is set or BSP is 1), then include in CRC, else exclude. Load. If DLE flag is not set, then set it. The DLE flag is cleared whenever processing for an outgoing character is finished (i.e., just before interrupt exit) unless the DLE flag was set by the current character (DLE). Thus the DLE flag will be set for the character following the DLE (the SCC) and then cleared. The character after the SCC may be DLE, which will again set the DLE flag.

ITB. Include in CRC and load. If BSP is 2 and DLE flag is not set, then treat as normal data, else set BSP = 1, save in previous text mode and set BSP = 3. Output “Reset Tx Underrun/EOM Latch” and “Reset Tx Int/DMA Pending” commands to USART register WR0, set the sync registers WR6 and WR7 to SYN SYN and set the BCC output flag for use by the external status interrupt as described above under ETX/ETB.

ENQ/EOT/NAK. If BSP is not 0, then include in CRC, else exclude in CRC. Load. If ENQ or this is last character in transmit buffer, then set BSP = 5.

SYN. If BSP is 2 and DLE flag is not set, then include in CRC, else exclude. Load.

“Stick”. If DLE flag is not set, then treat as “All others,” below. Otherwise, treat as “ENQ/EOT/NAK,” above.

“All others”. If BSP is not 0, then include in CRC, else exclude. Load.

If the BSP has a value of 3 through 7, actions are based on the BSP and not on the character code removed from the transmit buffer.

If BSP is 3, then exclude in CRC, load SYN and set BSP = 4.

If BSP is 4, then exclude in CRC, load SYN, reset Tx CRC generator (USART WR0) and set BSP = 1. Two SYN characters after ITB BCC BCC allow for proper synchronization after transparent text (DLE ITB). Also, the character before the reset Tx CRC generator command must be excluded from CRC, else the generator may not be completely reset.

If the BSP is 5, then load a trailing pad (hex FF) and set BSP = 0.

15. EIA (RS-232) Interface Considerations

The following signal lines on the EIA interface are used in BISYNC operation:

Input Lines from Modem
Pin	Use
3	Received Data
15	Transmit Clock Input
17	Receive Clock Input
5	Clear To Sent (CTS)
6	Data Set Ready (DSR)
8	Data Carrier Detect (DCD)
22	Ring Indicate
7	Signal Ground
1	Protective (frame) Ground
Output Lines to Modem
Pin	Use
2	Transmitted Data
4	Request To Send (RTS)
20	Data Terminal Ready (DTR)
14	New Sync
24	Transmit Clock Output

Usage of these signals is generally as described for the RS-232C standard. The “New Sync” signal (pin 14) is not standard and replaces secondary transmitted data of the standard. Also, some synchronous modems (e.g., Bell 201) output clock signals on pins 16 and 18, which conflict with outputs from the USART.

The new sync (NS) signal is only used in a full duplex 4-wire multi-drop installation where the USART is acting as the central station. In this case, the NS signal is turned on just as the first character (leading pad or SYN) is output and turned off just as the trailing pad output is started. The NS signal serves to immediately squelch the modem receiver clock decoder in preparation for a transmission from a different tributary station.

In the case where new sync operation is required (multi-drop tributary interface), the USART is jumpered to connect pin 14 to port B transmit data. Port B is then programmed in async mode with transmitter disabled and the send break bit (WR5 – bit 4) active (one). When NS is to be assembled, the send break bit is cleared to zero until the NS signal is to be turned off, just as the first trailing pad is output, then the send break bit on channel B is turned back on.

DTR is turned on after the USART program is loaded and initialized and left on at all times on an unswitched line. In switched line operation, DTR is turned off after a DISC (DLE EOT) is transmitted, which causes the modem to “hang up” the telephone line. A dial operation code (not described in this tutorial) will turn on DTR for switched line operation.

During any driver operation, the data set ready (DSR) signal is monitored on each receive or transmit interrupt. If it is off at the beginning of an operation or at any interrupt time, the “DSR lost” bit in the completion code is set, and the “Request incomplete” bit is cleared.

As described in the receive and transmit block operations, loss of DCD during receive or CTS during transmit will abort the operation in progress.

If external (modem) clocking is used, then both receive and transmit clocks are supplied by the modem on pins 15 and 17. If internal (business machine) clocking is used, then the transmit clock is supplied to the modem on pin 24. The modem echoes it back on pin 15. The modem supplies the receive clock on pin 17 in either case. Receive data is sampled on the positive to negative edge of receiver clock. Transmit data transitions are made on negative to positive transitions of transmit clock.

Ring Indicator (pin 22) is used only in switched line operation to indicate an incoming call.

In point to point (either station) full duplex 4 wire operation or for central station (tributary interface) in full duplex 4 wire multi-drop operation, RTS will be active at all times when in text mode after the USART program is loaded and initialized. Thus, CTS will be active whenever DSR is active.

In half-duplex 2 wire operation or for tributary station (host interface) in full duplex 4 wire multi-drop operation and the central station is using new sync, RTS will be turned on by the driver whenever the USART is initialized for transmit, and RTS is turned off when the USART is initialized for receive. The modem then turns on CTS after some delay after RTS becomes active and turns off CTS almost immediately after RTS becomes inactive.

A third mode is available for 4 wire connections where RTS is active all the time during text mode (master or slave) but will be turned off whenever EOT is sent or received. This is the appropriate mode of operation for multi-point tributary stations (host interface) in a link where the central host station modem is not using the new sync technique, because it will minimize turn around delays. If the central station is using new sync, then the half-duplex option should be chosen, even if the connection is 4 wire.

Please feel free to link to this tutorial but please let us know if you wish to re-publish all or portions of this document.

With 20+ years as a top software and firmware developer, Charles Wilde has acquired a combination of proven business smarts, mobile development skills and device engineering expertise that is hard to match. Charles no longer works on Bisync but is available to consult with you and your team about native code development in Android, Windows Mobile, Windows CE and other embedded systems. Wilde is author of the e-book, Porting Native Code to Android. He can be reached at AtonMail ( at ) aton.com. © 1981-2004 Aton International, Inc.

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